CPU pipeline
Stall
Write the code and design the chip that runs it.
You play both the programmer and the microarchitect, under a transistor budget. You watch instructions through pipeline stages, cache misses, mispredicts, stalls.
· Not playable yet — see the changelog
What you'll come away knowing
- What a load-use stall costs, and what forwarding buys back.
- Why a branch mispredict costs the whole fetch-to-resolve depth — and why a deeper pipeline makes it worse.
- That a DRAM access is roughly a hundred instructions of lost work.
- Why pointer chasing serializes cache misses while an array walk overlaps them.
- How a 2-bit predictor survives a loop exit that a 1-bit predictor mispredicts twice.
- Why the same code runs at wildly different speeds on sorted and unsorted data.
How the model works
This sim is still being built. The model, scenarios and visuals for the CPU pipeline are on the plan but not yet playable.
The shared engine it will run on is finished: deterministic fixed-timestep model in a Web Worker, checkpoints and seek, replayable share links, and the trace strip every sim uses.
Questions
When will it be playable?
Sims ship one at a time, each with at least eight scenarios, a full test suite and a landing page, before the next one starts. Check the changelog.